View L3GD20HTR_9036951.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. march 2013 docid023469 rev 2 1/52 52 l3gd20h mems motion sensor: three-axis digital output gyroscope datasheet - production data features ? wide supply voltage, 2.2 v to 3.6 v ? wide extended operating temperature range (from -40 c to 85 c) ? low voltage compatible ios, 1.8 v ? low power consumption ? embedded power-down ? sleep mode ? fast turn-on and wake-up ? three selectable full scales up to 2000 dps ? 16 bit rate value data output ? 8 bit temperature data output ? i 2 c/spi digital output interface ? 2 dedicated lines (1 interrupt, 1 data ready) ? user enable integrated high-pass filters ? embedded temperature sensor ? embedded 32 levels of 16 bit data output fifo ? high shock survivability ? ecopack ? rohs and ?green? compliant applications ? gaming and virtual reality input devices ? motion control with mmi (man-machine interface) ? gps navigation systems ? appliances and robotics description the l3gd20h is a low-power three-axis angular rate sensor. it includes a sensing element and an ic interface able to provide the measured angular rate to the external world through digital interface (i 2 c/spi). the sensing element is manufactured using a dedicated micromachining process developed by st to produce inertial sensors and actuators on silicon wafers. the ic interface is manufactured using a cmos process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the sensing element characteristics. the l3gd20h has a full scale of 245/500/2000 dps and is capable of measuring rates with a user selectable bandwidth. the l3gd20h is available in a plastic land grid array (lga) package and can operate within a temperature range from -40 c to +85 c. lga-16 (3x3x1 mm) table 1. device summary order code temperature range (c) package packing l3gd20h -40 to +85 lga-16 (3x3x1) tray L3GD20HTR -40 to +85 lga-16 (3x3x1) tape and reel www.st.com
contents l3gd20h 2/52 docid023469 rev 2 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.3 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.2 i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.2 zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.3 stream mode - dynamic stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.4 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2.5 bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.6 bypass-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.7 retrieve data from fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.8 fifo multiple read (burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 level-sensitive/edge sensitive/impulse sensitive data enable . . . . . . . . . 25 4.3.1 level sensitive trigger stamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3.2 edge sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3.3 impulse sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
docid023469 rev 2 3/52 l3gd20h contents 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.3 spi read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 ctrl1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 ctrl2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 ctrl3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.5 ctrl4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.6 ctrl5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.7 reference (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.8 out_temp (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.9 status (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.10 out_x_l (28h), out_x_h (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.11 out_y_l (2ah), out_y_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.12 out_z_l (2ch), out_z_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.13 fifo_ctrl (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.14 fifo_src (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.15 ig_cfg (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.16 ig_src (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.17 ig_ths_xh (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.18 ig_ths_xl (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.19 ig_ths_yh (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.20 ig_ths_yl (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.21 ig_ths_zh (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.22 ig_ths_zl (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.23 ig_duration (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
contents l3gd20h 4/52 docid023469 rev 2 7.24 low_odr (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
docid023469 rev 2 5/52 l3gd20h list of tables list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 table 6. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. i2c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. trigger stamping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. i2c terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 15. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 29 table 16. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 29 table 17. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 18. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 19. ctrl1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 20. ctrl1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 21. dr and bw configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 22. power mode selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 23. ctrl2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 24. ctrl2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 25. high pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 26. high pass filter cut off frequency configuration [hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 27. ctrl3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 28. ctrl3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 29. ctrl4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 30. ctrl4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 31. ctrl5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 32. ctrl5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 33. reference register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 34. reference register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 table 35. out_temp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 36. out_temp register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 37. status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 38. status description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 39. fifo_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 40. fifo_ctrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 41. fifo mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 42. fifo_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 43. fifo_src register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 44. ig_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 45. ig_cfg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 46. ig_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 47. ig_src description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 48. ig_ths_xh register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
list of tables l3gd20h 6/52 docid023469 rev 2 table 49. ig_ths_xh description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 50. ig_ths_xl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 51. ig_ths_xl description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 52. ig_ths_yh register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 53. ig_ths_yh description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 54. ig_ths_yl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 55. ig_ths_yl description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 56. ig_ths_zh register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 57. ig_ths_zh description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 58. ig_ths_zl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 59. ig_ths_zl description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 60. ig_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 61. ig_duration description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 62. low_odr register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 63. low_odr description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 64. lga 3x3x1.0 16l mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 table 65. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
docid023469 rev 2 7/52 l3gd20h list of figures list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. i2c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. l3gd20h electrical connections and external components values . . . . . . . . . . . . . . . . . . 17 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. stream mode with threshold interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. dynamic stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14. fifo multiple read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. trigger stamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 16. edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 17. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 19. multiple bytes spi read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 20. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 21. multiple bytes spi write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22. spi read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23. ig_sel and out_sel configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 24. wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 25. wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 26. lga 3x3x1.0 16l mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
block diagram and pin description l3gd20h 8/52 docid023469 rev 2 1 block diagram and pin description figure 1. block diagram the vibration of the structure is maintained by a drive circuitry in a feedback loop. the sensing signal is filtered and appears as digital signal at the output. 1.1 pin description figure 2. pin connection fifo trimming circuits reference mixer charge amp clock low-pass filter + x,y,z i2c spi cs scl/spc sda/sdi/sdo sdo/sa0 y+ z+ y- z- x+ x- driving mass feedback loop m u x a d d c i g i t a l f i l t e r i n g control logic & interrupt gen. int1 drdy/int2 den a d c t e m p e r a t u r e s e n s o r 1 2 & phase generator am12689v1 (top view) directions of the detectable angular rate 1 x vdd_io scl/spc sda/sdi/sdo sdo/sa0 res int1 drdy/int2 cs den cap res vdd 1 8 6 16 + z + x bottom view + y 5 13 9 res res gnd gnd 14 am12690v1
docid023469 rev 2 9/52 l3gd20h block diagram and pin description table 2. pin description pin# name function 1 vdd_io (1) 1. recommended 100 nf filter capacitor. power supply for i/o pins 2 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 3 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 4 sdo sa0 spi serial data output (sdo) i 2 c less significant bit of the device address (sa0) 5cs i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i2c disabled) 6 drdy/int2 data ready/fifo interrupt (fifo threshold/overrun/empty) 7 int1 programmable interrupt 8den (2) 2. connected to gnd if den is not used. gyroscope data enable 9 reserved connect to gnd 10 reserved connect to gnd 11 reserved connect to gnd or vdd 12 gnd 0 v supply 13 gnd 0 v supply 14 cap connect to gnd with ceramic capacitor (3) 3. 10 nf (+/-10%), 25 v. 1 nf minimum value has to be guaranteed under 12 v bias condition. 15 reserved connect to gnd or vdd 16 vdd (4) 4. recommended 100 nf plus 10 f capacitors. power supply
mechanical and electrical specifications l3gd20h 10/52 docid023469 rev 2 2 mechanical and electrical specifications 2.1 mechanical characteristics @ vdd = 3.0 v, t = 25 c unless otherwise noted (a) . a. the product is factory calibrated at 3.0 v. the operational power supply range is specified in table 4 . table 3. mechanical characteristics symbol parameter test condition min. typ. (1) max. unit fs measurement range user selectable 245 500 2000 dps so sensitivity 8.75 17.50 70.00 mdps/digit sodr sensitivity change vs. temperature (2) from -40 c to +85 c delta from t = 25 c 2 % dvoff digital zero-rate level fs = 2000 dps 25 dps offdr zero-rate level change vs temperature (3) fs = 2000 dps 0.04 dps/c nl non linearity (3) best fit straight line 0.2 % fs rn rate noise density (3) bw = 50 hz 0.011 odr digital output data rate (3) 11.9/23.7/ 47.3/94.7/ 189.4/ 378.8/ 757.6 hz top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. guaranteed by design. 3. the period (1/odr), length of time between two consecutive sampling, must be derived by the reciprocal of the maximum. and minimum odr limits: for example for odr = 189.4 hz, sampling period range will be within [4591 s, 6211 s] (where odr minimum and maximum have been approxim ated at 162 hz, 219 hz respectively). dps/ hz ()
docid023469 rev 2 11/52 l3gd20h mechanical and electrical specifications 2.2 electrical characteristics @ vdd =3.0 v, t=25 c unless otherwise noted (b) . b. the product is factory calibrated at 3.0 v. table 4. electrical characteristics symbol parameter test condition min. typ. (1) max. unit vdd supply voltage 2.2 3.0 3.6 v vdd_io i/o pins supply voltage (2) 1.71 vdd+0.1 v idd supply current 5.0 ma iddsl supply current in sleep mode (3) selectable by digital interface 2.5 ma iddpdn supply current in power- down mode selectable by digital interface 1 a vih digital high level input voltage 0.8*vdd_i o v vil digital low level input voltage 0.2*vdd_i o v ton turn-on time (4) lpf2 disabled odr = 190 hz 50 ms to p operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. it is possible to remove vdd maintaining vdd_io without blocking the communication busses, in this condition the measurement chain is powered off. 3. sleep mode introduces a faster turn-on time related to power down mode. 4. time to obtain stable sensitivity (within 5% of final value) after exiting pow er-down mode. it is guaranteed by design.
mechanical and electrical specifications l3gd20h 12/52 docid023469 rev 2 2.3 temperature sensor characteristics @ vdd =3.0 v, t=25 c unless otherwise noted (c) . c. the product is factory calibrated at 3.0 v. table 5. temperature sensor characteristics symbol parameter test condition min. typ. (1) max. unit tsdr temperature sensor output change vs temperature - -1 c/digit todr temperature refresh rate 1 hz top operating temperature range -40 +85 c 1. typical specifications are not guaranteed.
docid023469 rev 2 13/52 l3gd20h mechanical and electrical specifications 2.4 communication interface characteristics 2.4.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 3. spi slave timing diagram (d) table 6. spi slave timing values symbol parameter value (1) unit min. max. tc(spc) spi clock cycle 100 ns fc(spc) spi clock frequency 10 mhz tsu(cs) cs setup time 5 ns th(cs) cs hold time 20 tsu(si) sdi input setup time 5 th(si) sdi input hold time 15 tv(so) sdo valid output time 50 th(so) sdo output hold time 5 tdis(so) sdo output disable time 50 1. values are guaranteed at 10 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results, not tested in production. d. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output port. spc cs sd i sd o t su(cs) t v(so) t h(so) t h(si) t su(si) t h(cs) t dis(so) t c(spc) msb in msb out lsb out lsb in
mechanical and electrical specifications l3gd20h 14/52 docid023469 rev 2 2.4.2 i 2 c - inter ic control interface subject to general operating conditions for vdd and top. figure 4. i 2 c slave timing diagram (e) table 7. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min. max. min. max. f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3.45 0 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b (2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. 2. cb = total capacitance of one bus line, in pf. e. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. sda scl t f(sda) t su(sp) t w(scll) t su(sda) t r(sda) t su(sr) t h(st) t w(sclh) t h(sda) t r(scl) t f(scl) t w(sp:sr) start repeated start stop start
docid023469 rev 2 15/52 l3gd20h mechanical and electrical specifications 2.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v. table 8. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v t stg storage temperature range -40 to +125 c sg acceleration g for 0.1 ms 10,000 g esd electrostatic discharge protection 2 (hbm) kv vin input voltage on any control pin (including cs,scl/spc,sda/sdi/sdo,sdo/sa0,den) 0.3 to vdd_io +0.3 v this is a mechanical shock sensitive device, improper handling can cause permanent damage to the part. this is an esd sensitive device, improper handling can cause permanent damage to the part.
mechanical and electrical specifications l3gd20h 16/52 docid023469 rev 2 2.6 terminology 2.6.1 sensitivity an angular rate gyroscope is a device that produces a positive-going analog output for counterclockwise rotation around the sensitive axis considered. sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. this value changes very little over temperature and time. 2.6.2 zero-rate level zero-rate level describes the actual output signal if there is no angular rate present. zero- rate level of precise mems sensors is, to some extent, a result of stress to the sensor and therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. 2.7 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resistance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www.st.com/mems .
docid023469 rev 2 17/52 l3gd20h application hints 3 application hints figure 5. l3gd20h electrical connections and external components values power supply decoupling capacitors (100 nf + 10 f) should be placed as near as possible to the device (common design practice). if vdd and vdd_io are not connected together, 100 nf and 10 f decoupling capacitors must be placed between vdd and common ground while 100 nf between vdd_io and common ground. capacitors should be placed as near as possible to the device (common design practice). (top view) 1 x + z directions of the detectable angular rates + x + y den vdd 10f gnd 100nf vdd_io int1 drdy/int2 scl/spc 1 8 5 5 13 top view 6 14 16 9 9 gnd c1 10nf(25v)* gnd * sda/sdi/sdo c1 must guarantee 1nf value under 12v bias condition gnd sdo cs 100nf vdd i2c bus rpu rpu = 10kohm scl/spc sda_sdi_sdo pull-up to be added when i2c interface is used gams080220130927fsr
digital main blocks l3gd20h 18/52 docid023469 rev 2 4 digital main blocks 4.1 block diagram figure 6. block diagram 4.2 fifo l3gd20h embeds 32 slots of 16-bit data fifo for each of the three output channels: yaw, pitch and roll. this allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wakeup only when needed and burst the significant data out from the fifo. this buffer can work accordingly to seven different modes: bypass mode, fifo-mode, stream mode, stream-to-fifo mode, bypass-to-stream, dynamic-stream, bypass-to-fifo. each mode is selected by the fm2:0 bits in fifo_ctrl register. programmable fifo threshold level, fifo empty or fifo overrun events are available on fifo_src register and can be set to generate dedicated interrupts on drdy/int2 pin. fifo_src(empty) is equal to '1' when no samples are available. fifo_src(fth) goes to '1' if a new data arrives and fifo_src(fss4:0) is greater than or equal to fifo threshold configured to fth4:0 into fifo_ctrl (2eh). fifo_src(fth) goes to '0' if reading yaw, pitch and roll data slot from fifo and fifo_src(fss4:0) is minor than or equal to fifo_ctrl(fth4:0). adc lpf1 hpf 0 1 hpen lpf2 10 11 01 00 out_sel datareg 00 11 10 01 interrupt generator int_sel i 2 c spi int1 scr reg conf reg fifo 32x16x3 am07230v1
docid023469 rev 2 19/52 l3gd20h digital main blocks fifo_src(ovrn) is equal to '1' if a fifo slot is overwritten. fifo feature is enabled writing to '1' ctrl5(fifo_en). to guarantee the switching into and out of fifo mode discard the first sample aquired. 4.2.1 bypass mode in bypass mode (fifo_ctrl(fm2:0) = 000), the fifo is not operational and it remains empty. bypass mode is also used to reset the fifo when in fifo-mode. as described in the next figure, for each channel only the first address is used. when a new data is available the old one is overwritten. figure 7. bypass mode 4.2.2 fifo mode in fifo mode (fifo_ctrl(fm2:0) = 001) data from yaw, pitch and roll channels are stored into the fifo until it is full. to reset fifo content bypass mode should be written in fifo_ctrl(fm2:0) '000' value. after this reset command it is possible to restart fifo mode writing fifo_ctrl(fm2:0) the value '001'. fifo buffer can memorize 32 yaw, pitch and roll data, but the depth of the fifo can be reduced by means of ctrl5(stoponfth) bit setting to '1' stoponfth bit, fifo depth is limited to fifo_ctrl(fth4:0) - 1. a fifo threshold interrupt can be enabled (int2_orun bit into ctrl3 (22h)) in order to be raised when the fifo is filled to the level specified into the fth4:0 bits of fifo_ctrl (2eh). when fifo threshold interrupt occurs, the first data has been overwritten and the fifo stops collecting data from the input channels. [ \ l ] \ [ \ ] [ \ ] [ \ ] [ l \ l ] l hpsw\ $0y
digital main blocks l3gd20h 20/52 docid023469 rev 2 figure 8. fifo mode 4.2.3 stream mode - dynamic stream stream mode (fifo_ctrl(fm2:0) = 010) provides continuous fifo update: as new data arrives the older is discarded. an overrun interrupt can be enabled, ctrl3(int2_orun)= '1', in order to read the whole fifo content at once. if in the application no data can be lost and it is not possible to read at least one sample for each axis within one odr period, a fifo threshold interrupt can be enabled in order to read partially the fifo and let free memory slots for data incoming. setting the fifo_ctrl(fth4:0) to n value, the number of yaw, pitch and roll data samples that should be read at fifo threshold interrupt rising is up to (n+1). [ \ l ] \ [ \ ] [ \ ] [ \ ] [ l \ l ] l $0y
docid023469 rev 2 21/52 l3gd20h digital main blocks figure 9. stream mode in the latter case reading all fifo content before an overrun interrupt has occurred, the first data read is equal to the last already read in previous burst, so the number of new data available in fifo depends on previous reading (see fifo_src behavior depicted in next figures). figure 10. stream mode with threshold interrupt enable in dynamic-stream mode (fifo_ctrl(fm2:0) = 110) after emptying the fifo the first new sample that arrives becomes the first to be read in subsequent read burst. in this way in [ \ ] [ \ ] [ \ ] [ \ ] [ l \ l ] l [ \ ] $0y gams310120131021fsr
digital main blocks l3gd20h 22/52 docid023469 rev 2 dynamic-stream mode (fifo_ctrl(fm2:0) = 110) the number of new data available in fifo does not depend on previous reading. in dynamic-stream mode fifo_src(fss4:0) + 1 is the number of new x, y and z samples available in the fifo buffer. stream mode is intended to be used reading all 32 samples of fifo within an odr after receiving an overrun signal. dynamic-stream is intended to be used to read fifo_src(fss4:0) + 1 samples when it is not possible to guarantee data reading within an odr. in dynamic-stream mode fifo_ctrl(fth4:0) setting should be between 1 and 30. also a fifo threshold interrupt ctrl3(int2_fth) can be enabled in order to read data from the fifo and let free memory slot for data incoming. setting the fifo_ctrl(fth4:0) to n value, the number of x, y and z data samples that should be read at fifo threshold interrupt rising, in order to read the whole fifo content, is n + 2. figure 11. dynamic stream mode 4.2.4 stream-to-fifo mode in stream-to-fifo mode (fifo_ctrl(fm2:0) = 011), fifo behavior changes according to ig_src(ia) bit. when ig_src(ia) bit is equal to '1' fifo operates in fifo-mode, when ig_src(ia) bit is equal to '0' fifo operates in stream mode. interrupt generator should be set to the desired configuration by means of ig_cfg, ig_ths_xh, ig_ths_xl, ig_ths_yh, ig_ths_yl, ig_ths_zh and ig_ths_zl. ig_cfg(lir) bit should be put to '1' in order to have latched interrupt. gams310120131023fsr
docid023469 rev 2 23/52 l3gd20h digital main blocks figure 12. trigger stream mode 4.2.5 bypass-to-stream mode in bypass-to-stream mode (fifo_ctrl(fm2:0) = '100'), yaw, pitch and roll measurement storage inside fifo operates in stream mode when ig_src (ia) is equal to '1', otherwise fifo content is reset (bypass mode) . interrupt generator should be set to the desired configuration by means of ig_cfg, ig_ths_xh, ig_ths_xl, ig_ths_yh, ig_ths_yl, ig_ths_zh and ig_ths_zl. ig_cfg(lir) bit should be put to '1' in order to have latched interrupt. figure 13. bypass-to-stream mode x 0 y i z 0 y 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i empty bypass mode stream mode trigger event x 0 y 0 z 0 x 1 y 1 z 1 x 2 y 2 z 2 x 31 y 31 z 31 x i ,y i ,z i x 30 y 30 z 30 am07235v1 [ \ l ] \ [ \ ] [ \ ] [ \ ] [ l \ l ] l (psw\ %\sdvvprgh 6wuhdpprgh 7uljjhuhyhqw [ \ ] [ \ ] [ \ ] [ \ ] [ l \ l ] l [ \ ] $0y
digital main blocks l3gd20h 24/52 docid023469 rev 2 4.2.6 bypass-to-fifo mode in bypass-to-fifo mode (fifo_ctrl(fm2:0) = '111', fifo behavior changes according to ig_src(ia) bit. when ig_src(ia) bit is equal to '1' fifo operates in fifo-mode, when ig_src(ia) bit is equal to '0' fifo operates in bypass mode (fifo content reset). if a latched interrupt is generated fifo starts collecting data until the first data into the fifo- buffer is overwritten. interrupt generator should be set to the desired configuration by means of ig_cfg, ig_ths_xh, ig_ths_xl, ig_ths_yh, ig_ths_yl, ig_ths_zh and ig_ths_zl. ig_cfg (lir) bit should be put to '1' in order to have latched interrupt. 4.2.7 retrieve data from fifo fifo data is read through out_x_l and out_x_h (addr reg 28h and 29h), out_y_l out_y_h (addr reg 2ah and 2bh) and out_z_l and out_z_h (addr reg 2ch and 2dh) registers. a read operation by means of serial interface of out_x, out_y or out_z output registers provides the data stored into the fifo. each time data is read from the fifo, the oldest x, y and z data are placed into the out_x, out_y and out_z registers and both single read and read_burst operations can be used. 4.2.8 fifo multiple read (burst) starting from the addr 28h multiple read can be performed. once the reading reaches the addr 2dh the system automatically restarts from the addr. 28h. figure 14. fifo multiple read x,y,z out_z read #1 (2a-2b) (2c-2d) out_y (28-29) out_x x,y,z read #n out_z (2a-2b) (2c-2d) out_y (28-29) out_x gams290120131638fsr
docid023469 rev 2 25/52 l3gd20h digital main blocks 4.3 level-sensitive/edge sensitive/impulse sensitive data enable l3gd20h allows external trigger level recognition through enabling extren and lvlen bits into ctrl2 (21h) and impen bit into ctrl4 (23h). three different modes can be used: level, edge or impulse sensitive trigger. figure 15. trigger stamping 4.3.1 level sensitive trigger stamping level sensitive trigger can be enabled by setting to ?1? the lvlen bit into ctrl2 (21h) while extren bit into ctrl2 (21h) and impen bit into ctrl4 (23h) have to be set to ?0?. once enabled, den level replaces the lsb of x, y or z axes configurable through xen, yen, zen bits into ctrl1 (20h). data is stored inside the fifo with the internal selected odr. 4.3.2 edge sensitive trigger edge sensitive trigger can be enabled by setting to ?1? the extren bit into ctrl2 (21h) while lvlen bit into ctrl2 (21h) and impen bit into ctrl4 (23h) have to be set to ?0?. table 9. trigger stamping mode lvlen extren impen trigger stamping mode 1 0 0 level sensitive trigger 0 1 0 edge sensitive trigger 1 0 1 impulse sensitive trigger x i (15-1) x i ,y i ,z i d e n y i (15-0) z i (15-0) x i-n+1 n d e (15-1) y i-n+1 (15-0) z i-n+1 (15-0) x i (15-0) x i ,y i ,z i d e n y i (15-1) z i (15-0) x i (15-0) x i ,y i ,z i n d e y i (15-0) z i (15-1) x i-n+1 n d e (15-0) y i-n+1 (15-0) z i-n+1 (15-1) x i-n+1 n d e y i-n+1 z i-n+1 (15-0) (15-1) (15-0) level-sensitive trigger enabled on y-axis yen=1, xen=zen=0 level-sensitive trigger enabled d on x-axis xen=1,yen=zen=0 level-sensitive trigger enabled on z-axis zen=1, xen=yen=0 gams290120131645fsr
digital main blocks l3gd20h 26/52 docid023469 rev 2 once enabled, fifo is filled with the pitch, roll and yaw data on the rising edge of den input signal. when odr selected is 800 hz, maximum den sample frequency is f den =1/t den = 400 hz. figure 16. edge-sensitive trigger 4.3.3 impulse sensitive trigger impulse sensitive trigger can be enabled by setting to ?1? lvlen bit into ctrl2 (21h) and impen bit into ctrl4 (23h) while the extren bit into ctrl2 (21h) has to be set to ?0?. if the duration of the den pulse is shorter than the selected odr, the impulse sensitive trigger functionality has to be enabled. gams310120131026fsr
docid023469 rev 2 27/52 l3gd20h digital interfaces 5 digital interfaces the registers embedded inside the l3gd20h may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pins. to select/exploit the i 2 c interface, cs line must be tied high (i.e connected to vdd_io). 5.1 i 2 c serial interface the l3gd20h i 2 c is a bus slave. the i 2 c is employed to write data into registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both the lines must be connected to vdd_io through external pull-up resistor. when the bus is free both the lines are high. the i 2 c interface is compliant with fast mode (400 khz) i 2 c standards as well as with the normal mode. table 10. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) scl/spc i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi/sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo/sa0 spi serial data output (sdo) i 2 c less significant bit of the device address table 11. i 2 c terminology term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
digital interfaces l3gd20h 28/52 docid023469 rev 2 5.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the l3gd20h is 110101xb. sdo/sa0 pin can be used to modify less significant bit of the device address. if sdo/sa0 pin is connected to voltage supply lsb is ?1? (address 1101011b) else if sdo/sa0 pin is connected to ground lsb value is ?0? (address 1101010b). this solution permits to connect and address two different gyroscopes to the same i 2 c bus. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the l3gd20h behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, a 8-bit sub-address will be transmitted: the 7 lsb represent the actual register address while the msb enables address auto increment. if the msb of the sub field is 1, the sub (register address) will be automatically incremented to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition will have to be issued after the two sub-address bytes; if the bit is ?0? (write) the master will transmit to the slave with direction unchanged. ta ble 12 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 12. sad+read/write patterns command sad[6:1] sad[0] = sdo r/w sad+r/w read 110101 0 1 11010101 (d5h) write 110101 0 0 11010100 (d4h) read 110101 1 1 11010111 (d7h) write 110101 1 0 11010110 (d6h) table 13. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak
docid023469 rev 2 29/52 l3gd20h digital interfaces data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of first register to be read. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. in order to disable the i2c block it is needed to write '1' in bit 3 of register located in address 39h. 5.2 spi bus interface the spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo . table 14. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 15. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 16. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data
digital interfaces l3gd20h 30/52 docid023469 rev 2 figure 17. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple bytes read/write. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in latter case, the chip will drive sdo at the start of bit 8. bit 1 : ms bit. when 0, the address will remain unchanged in multiple read/write commands. when 1, the address will be auto incremented in multiple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that will be written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). in multiple read/write commands further blocks of 8 clock periods will be added. when ms bit is 0 the address used to read/write data remains the same for every block. when ms bit is 1 the address used to read/write data is incremented at every block. the function and the behavior of sdi and sdo remain unchanged. cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 do7do6do5do4do3do2do1do0 ms am10129v1
docid023469 rev 2 31/52 l3gd20h digital interfaces 5.2.1 spi read figure 18. spi read protocol the spi read command is performed with 16 clock pulses. multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). bit 16-... : data do(...-8). further data in multiple byte reading. figure 19. multiple bytes spi read protocol (2 bytes example) cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms am10130v1 cs sp c sdi sd o rw do7do6do5do4do3do2 do1do0 ad5 ad4 ad 3 ad2 ad1 ad0 do 15 do 14 do 13 do 12 do 11 do 10 d o9 d o8 ms am10131v1
digital interfaces l3gd20h 32/52 docid023469 rev 2 5.2.2 spi write figure 20. spi write protocol the spi write command is performed with 16 clock pulses. multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that will be written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writing. figure 21. multiple bytes spi write protocol (2 bytes example) cs spc sdi rw di7di6di5di4di3di2di1di0 ad5 ad 4 ad 3 ad2 ad 1 ad0 ms am10132v1 cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad 0 di 7 d i6 di 5 d i4 di 3 di 2 di 1 di 0 di 15 d i1 4 di 13 d i1 2 di 11 di 10 di 9 di 8 ms am10133v1
docid023469 rev 2 33/52 l3gd20h digital interfaces 5.2.3 spi read in 3-wires mode figure 22. spi read protocol in 3-wires mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that will be read from the device (msb first). multiple read command is also available in 3-wires mode. cs spc sdi/o rw do7do6do5do4do3do2do1do0 ad5 ad 4 ad 3 ad2 ad1 ad 0 ms am10134v1
output register mapping l3gd20h 34/52 docid023469 rev 2 6 output register mapping the table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: table 17. register address map name type register address default hex binary reserved - 00-0e - - who_am_i r 0f 000 1111 11010111 reserved - 10-1f - - ctrl1 rw 20 010 0000 00000111 ctrl2 rw 21 010 0001 00000000 ctrl3 rw 22 010 0010 00000000 ctrl4 rw 23 010 0011 00000000 ctrl5 rw 24 010 0100 00000000 reference rw 25 010 0101 00000000 out_temp r 26 010 0110 output status r 27 010 0111 output out_x_l r 28 010 1000 output out_x_h r 29 010 1001 output out_y_l r 2a 010 1010 output out_y_h r 2b 010 1011 output out_z_l r 2c 010 1100 output out_z_h r 2d 010 1101 output fifo_ctrl rw 2e 010 1110 00000000 fifo_src r 2f 010 1111 output ig_cfg rw 30 011 0000 00000000 ig_src r 31 011 0001 output ig_ths_xh rw 32 011 0010 00000000 ig_ths_xl rw 33 011 0011 00000000 ig_ths_yh rw 34 011 0100 00000000 ig_ths_yl rw 35 011 0101 00000000 ig_ths_zh rw 36 011 0110 00000000 ig_ths_zl rw 37 011 0111 00000000 ig_duration rw 38 011 1000 00000000 low_odr rw 39 011 1001 00000000
docid023469 rev 2 35/52 l3gd20h output register mapping registers marked as reserved must not be changed. the writing to those registers may cause permanent damages to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered-up.
register description l3gd20h 36/52 docid023469 rev 2 7 register description the device contains a set of registers which are used to control its behavior and to retrieve angular rate data. the registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 7.1 who_am_i (0fh) device identification register. 7.2 ctrl1 (20h) dr<1:0> is used to set odr selection. bw <1:0> is used to set bandwidth selection. in the following table are reported all frequency resulting in combination of dr / bw bits. table 18. who_am_i register 11010111 table 19. ctrl1 register (1) 1. xen, yen, zen enable x, yor z register in level s ensitive trigger mode. once lvlen bit = 1, den level replaces the lsb of x, y or z axes and all axis are available for reading. dr1 dr0 bw1 bw0 pd zen xen yen table 20. ctrl1 description dr1-dr0 output data rate selection. refer to table 21 bw1-bw0 bandwidth selection. refer to table 21 pd power mode. default value: 0. refer to table 0= power down 1= normal mode (for sleep mode set {pd:zen:yen:xen} to {1000}) zen z axis enable. default value: 1 (0: z axis disabled; 1: z axis enabled) yen y axis enable. default value: 1 (0: y axis disabled; 1: y axis enabled) xen x axis enable. default value: 1 (0: x axis disabled; 1: x axis enabled)
docid023469 rev 2 37/52 l3gd20h register description combination of pd, zen, yen, xen are used to set device in different modes (power down / normal / sleep mode) according with the following table. table 21. dr and bw configuration setting low_odr (1) 1. this bit is described in re gister low_odr (39h register). dr <1:0> bw <1:0> odr [hz] cut-off [hz] (2) 2. values in the table are indicative and they c an vary proportionally with the specific odr value. 1 000012.5n.a. 1 000112.5n.a. 1 001012.5n.a. 1001112.5n.a. 1 010025n.a. 1 010125n.a. 1 011025n.a. 1011125n.a. 11x005016.6 11x015016.6 11x105016.6 11x115016.6 0 000010012.5 0 000110025 0 001010025 0001110025 0 010020012.5 0 0101200- 0 0110200- 0011120070 0 100040020 0 100140025 0 101040050 01011400110 0110080030 0110180035 01110800- 0 1111800100
register description l3gd20h 38/52 docid023469 rev 2 7.3 ctrl2 (21h) table 22. power mode selection configuration mode pd zen yen xen power down 0 - - - normal 1 - - - sleep 1 0 0 0 table 23. ctrl2 register extren lvlen hpm1 hpm0 hpcf3 hpcf2 hpcf1 hpcf0 table 24. ctrl2 description extren edge sensitive trigger enable: default value: 0 (0: external trigger disabled; 1: external trigger enabled) lvlen level sensitive trigger enable: default value: 0 (0: level sensitive trigger disabled; 1: level sensitive trigger enabled) hpm1- hpm0 high pass filter mode selection. default value: 00 refer to table 25 hpcf3- hpcf0 high pass filter cut off frequency selection. default value: 0000 refer to table 26 table 25. high pass filter mode configuration hpm1 hpm0 high pass filter mode 0 0 normal mode (reset reading reference 25h register) 0 1 reference signal for filtering 10normal mode 1 1 autoreset on interrupt event table 26. high pass filter cut off frequency configuration [hz] (1) hpcf3-0 odr=12.5 hz odr=25 hz odr=50 hz odr =100 hz odr =200 hz odr =400 hz odr =800 hz 00001248153056 0001 0.5 1 2 4 8 15 30 0010 0.2 0.5 1 2 4 8 15 0011 0.1 0.2 0.5 1 2 4 8
docid023469 rev 2 39/52 l3gd20h register description 7.4 ctrl3 (22h) 7.5 ctrl4 (23h) 0100 0.05 0.1 0.2 0.5 1 2 4 0101 0.02 0.05 0.1 0.2 0.5 1 2 0110 0.01 0.02 0.05 0.1 0.2 0.5 1 0111 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1000 0.002 0.005 0.01 0.02 0.05 0.1 0.2 1001 0.001 0.002 0.005 0.01 0.02 0.05 0.1 1. values in the table are indicative and they can vary proportionally with the specific odr value table 26. high pass filter cut off frequency configuration [hz] (1) (continued) hpcf3-0 odr=12.5 hz odr=25 hz odr=50 hz odr =100 hz odr =200 hz odr =400 hz odr =800 hz table 27. ctrl3 register int1_ig int1_boot h_lactive pp_od int2_drdy int2_fth int2_orun int2_empty table 28. ctrl3 description int1_ig interrupt enable on int1 pin. default value 0. (0: disable; 1: enable) int1_boot boot status available on int1 pin. default value 0. (0: disable; 1: enable) h_lactive interrupt active configuration on int. default value 0. (0: high; 1:low) pp_od push- pull / open drain. default value: 0. (0: push-pull; 1: open drain) int2_drdy date ready on drdy/int2 pin. default value 0. (0: disable; 1: enable) int2_fth fifo threshold interrupt on drdy/int2 pin. default value: 0. (0: disable; 1: enable) int2_orun fifo overrun interrupt on drdy/int2 pin. default value: 0. (0: disable; 1: enable) int2_empty fifo empty interrupt on drdy/int2 pin. default value: 0. (0: disable; 1: enable) table 29. ctrl4 register bdu ble fs1 fs0 impen st2 st1 sim table 30. ctrl4 description bdu block data update. default value: 0 (0: continuos update; 1: output registers not updated until msb and lsb read- ing) ble big/little endian data selection. default value 0. (0: data lsb @ lower address; 1: data msb @ lower address)
register description l3gd20h 40/52 docid023469 rev 2 7.6 ctrl5 (24h) fs1-fs0 full scale selection. default value: 00 (00: 245 dps; 01: 500 dps; 1x: 2000 dps) impen level sensitive latched enable. default value: 0 (0: level sensitive latched disabled; 1: level sensitive latched enabled) st2-st1 self-test enable. default value: 00 00 = normal mode (default) 01 = self-test 0 (+) 10 = unused 11 = self-test 1(-) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface). table 30. ctrl4 description (continued) table 31. ctrl5 register boot fifo_en stoponfth hpen ig_sel1 ig_sel0 out_sel1 out_sel0 table 32. ctrl5 description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content (1) ) 1. boot request is executed as soon as internal oscillator is turned-on. it is possibile to set bit while in power- down mode, in this case it will be served at the next normal mode or sleep mode. fifo_en fifo enable. default value: 0 (0: fifo disable; 1: fifo enable) stoponfth sensing chain fifo stop values memorization at fifo threshold. default value: 0 0 = fifo depth is not limited (32 digital words per axis) 1 = fifo depth is limited to fifo threshold which is defined in fifo_ctrl (2eh register) hpen high pass filter enable. default value: 0 (0: hpf disabled; 1: hpf enabled see figure 23. ) ig_sel1-ig_sel0 int generator selection configuration. default value: 00 (see figure 23. ) out_sel1-out_- sel0 out selection configuration. default value: 00 (see figure 23. )
docid023469 rev 2 41/52 l3gd20h register description figure 23. ig_sel and out_sel configuration block diagram 7.7 reference (25h) 7.8 out_temp (26h) adc lpf1 hpf 0 1 hpen lpf2 10 11 01 00 out_sel <1:0> datareg fifo 32x16x3 00 11 10 01 interrupt generator int1_sel <1:0> am08592v1 table 33. reference register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 34. reference register description ref 7-ref0 digital high pass filter reference value. default value: 0 table 35. out_temp register temp7 temp6 temp5 temp4 temp3 temp2 temp1 temp0 table 36. out_temp register description temp7-temp0 temperature data (-1lsb/deg with 8 bit resolution). the value is expressed as two?s complement.
register description l3gd20h 42/52 docid023469 rev 2 7.9 status (27h) 7.10 out_x_l (28h), out_x_h (29h) x-axis angular rate data. the value is expressed as two?s complement. 7.11 out_y_l (2ah), out_y_h (2bh) y-axis angular rate data. the value is expressed as two?s complement. 7.12 out_z_l (2ch), out_z_h (2dh) z-axis angular rate data. the value is expressed as two?s complement. 7.13 fifo_ctrl (2eh) table 37. status register zyxor zor yor xor zyxda zda yda xda table 38. status description zyxor x, y, z -axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data has overwritten the previous one before it was read) zor z axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new data for the z-axis has overwritten the previous one) yor y axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new data for the y-axis has overwritten the previous one) xor x axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new data for the x-axis has overwritten the previous one) zyxda x, y, z -axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z axis new data available. default value: 0 (0: a new data for the z-axis is not yet available; 1: a new data for the z-axis is available) yda y axis new data available. default value: 0 (0: a new data for the y-axis is not yet available;1: a new data for the y-axis is available) xda x axis new data available. default value: 0 (0: a new data for the x-axis is not yet available; 1: a new data for the x-axis is available) table 39. fifo_ctrl register fm2 fm1 fm0 fth4 fth3 fth2 fth1 fth0
docid023469 rev 2 43/52 l3gd20h register description 7.14 fifo_src (2fh) 7.15 ig_cfg (30h) table 40. fifo_ctrl register description fm2-fm0 fifo mode selection. default value: 000 (see table 41 ) fth4-fth0 fifo threshold setting. default value: 0 table 41. fifo mode configuration fm2 fm1 fm0 fifo mode 000bypass mode 001fifo mode 010stream mode 011stream-to-fifo mode 100bypass-to-stream mode 110dynamic stream mode 111bypass-to-fifo mode table 42. fifo_src register fth ovrn empty fss4 fss3 fss2 fss1 fss0 table 43. fifo_src register description fth fifo threshold status. (0: fifo filling is lower than fth level; 1: fifo filling is equal or higher than fth level) ovrn overrun bit status. (0: fifo is not completely filled; 1:fifo is completely filled) empty fifo empty bit. ( 0: fifo not empty; 1: fifo empty) fss4-fss0 fifo stored data level of the unread samples table 44. ig_cfg register and/or lir zhie zlie yhie ylie xhie xlie
register description l3gd20h 44/52 docid023469 rev 2 configuration register for interrupt source. 7.16 ig_src (31h) table 45. ig_cfg description and/or and/or combination of interrupt events. default value: 0 (0: or combination of interrupt events 1: and combination of interrupt events lir latch interrupt request. default value: 0 (0: interrupt request not latched; 1: interrupt request latched) cleared by reading ig_src reg. zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured angular rate value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured angular rate value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured angular rate value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured angular rate value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured angular rate value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured angular rate value lower than preset threshold) table 46. ig_src register 0 ia zhzlyhylxhxl table 47. ig_src description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred)
docid023469 rev 2 45/52 l3gd20h register description interrupt source register. read only register. reading at this address clears ig_src ia bit (and eventually the interrupt signal on int1 pin) and allows the refresh of data in the ig_src register if the latched option was chosen. 7.17 ig_ths_xh (32h) 7.18 ig_ths_xl (33h) 7.19 ig_ths_yh (34h) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 47. ig_src description table 48. ig_ths_xh register dcrm thsx14 thsx13 thsx12 thsx11 thsx10 thsx9 thsx8 table 49. ig_ths_xh description dcrm interrupt generation counter mode selection. default value: 0 0 = reset 1 = decrement thsx14 - thsx8 interrupt threshold on x axis. default value: 000 0000 table 50. ig_ths_xl register thsx7 thsx6 thsx5 thsx4 thsx3 thsx2 thsx1 thsx0 table 51. ig_ths_xl description thsx7 - thsx0 interrupt threshold on x axis. default value: 0000 0000 table 52. ig_ths_yh register - thsy14 thsy13 thsy12 thsy11 thsy10 thsy9 thsy8 table 53. ig_ths_yh description thsy14 - thsy8 interrupt threshold on y axis. default value: 000 0000
register description l3gd20h 46/52 docid023469 rev 2 7.20 ig_ths_yl (35h) 7.21 ig_ths_zh (36h) 7.22 ig_ths_zl (37h) 7.23 ig_duration (38h) d6 - d0 bits set the minimum duration of the interrupt event to be recognized. duration steps and maximum values depend on the odr chosen. table 54. ig_ths_yl register thsy7 thsy6 thsy5 thsy4 thsy3 thsy2 thsy1 thsy0 table 55. ig_ths_yl description thsy7 - thsy0 interrupt threshold on y axis. default value: 0000 0000 table 56. ig_ths_zh register - thsz14 thsz13 thsz12 thsz11 thsz10 thsz9 thsz8 table 57. ig_ths_zh description thsz14 - thsz8 interrupt threshold on z axis. default value: 000 0000 table 58. ig_ths_zl register thsz7 thsz6 thsz5 thsz4 thsz3 thsz2 thsz1 thsz0 table 59. ig_ths_zl description thsz7 - thsz0 interrupt threshold on z axis. default value: 0000 0000 table 60. ig_duration register wait d6 d5 d4 d3 d2 d1 d0 table 61. ig_duration description wait wait enable. default value: 0 (0: disable; 1: enable) d6 - d0 duration value. default value: 000 0000
docid023469 rev 2 47/52 l3gd20h register description wait bit has the following meaning: wait =?0?: the interrupt falls immediately if signal crosses the selected threshold wait =?1?: if signal crosses the selected threshold, the interrupt falls after a number of samples equal to the duration counter register value. figure 24. wait disabled figure 25. wait enabled
register description l3gd20h 48/52 docid023469 rev 2 7.24 low_odr (39h) table 62. low_odr register -- -- drdy_hl 0 (1) 1. these bits must be set to ?0? for proper working of the device. i2c_dis sw_res 0 (1) low_odr table 63. low_odr description drdy_hl drdy/int2 pin active level. default value: 0 0 = drdy active high 1 = drdy active low i2c_dis 0 = both the i2c and spi interfaces enabled (default) 1 = spi only sw_res software reset. default value: 0 0 = normal mode 1 = reset device (this bit is cleared by hardware after next flash boot) low_odr low speed odr. default value: 0 refer to ta ble 21 dr and bw configuration setting: for odr and bandwidth configuration on ctrl1 register 0 = low speed odr disabled 1 = low speed odr enabled
docid023469 rev 2 49/52 l3gd20h package information 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. table 64. lga 3x3x1.0 16l mechanical data dim. mm min. typ. max. a1 1 a2 0.785 a3 0.200 d1 2.850 3.000 3.150 e1 2.850 3.000 3.150 l1 1.000 1.060 l2 2.000 2.060 n1 0.500 n2 1.000 m 0.040 0.100 p1 0.875 p2 1.275 t1 0.290 0.350 0.410 t2 0.190 0.250 0.310 d0.150 k0.050
package information l3gd20h 50/52 docid023469 rev 2 figure 26. lga 3x3x1.0 16l mechanical drawing 7983231_m
docid023469 rev 2 51/52 l3gd20h revision history 9 revision history table 65. document revision history date revision changes 20-jul-2012 1 initial release. 05-mar-2013 2 added chapter 3: application hints , chapter 6: output register mapping and chapter 7: register description updated chapter 4.2: fifo .
l3gd20h 52/52 docid023469 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of L3GD20HTR

	To Download L3GD20HTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .